CORC

在结果中检索

CORC

浏览/检索结果: 共46条，第1-10条 帮助

已选(0)清除 条数/页：   排序方式：
Suppression of Filament Overgrowth in Conductive Bridge Random Access Memory by TaO/TaO Bi-Layer Structure. 期刊论文
Nanoscale research letters, 2019, 卷号: Vol.14 No.1, 页码: 111
作者:  Danian Dong;  Xiulong Wu;  Tiancheng Gong;  Ming Liu;  Hangbing Lv
收藏  |  浏览/下载：36/0  |  提交时间：2019/04/24
pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology 期刊论文
Nanoscale Research Letters, 2017
作者:  Zhao C(赵超);  Wang GL(王桂磊);  Luo J(罗军);  Liu JB(刘金彪);  Yang T(杨涛)
收藏  |  浏览/下载：15/0  |  提交时间：2018/07/05
CMOS-Compatible Fabrication for Photonic Crystal-Based Nanofluidic Structure 期刊论文
Nanoscale Research Letters, 2017, 卷号: 12, 期号: 1, 页码: 103-
作者:  Peng, Wang;  Chen, Youping;  Ai, Wu;  Zhang, Dailin*;  Song, Han
收藏  |  浏览/下载：18/0  |  提交时间：2019/12/04
Low-Leakage ESD Power Clamp Design With Adjustable Triggering Voltage for Nanoscale Applications 期刊论文
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017
Lu, Guangyi; Wang, Yuan; Wang, Yize; Zhang, Xing
收藏  |  浏览/下载：7/0  |  提交时间：2017/12/03
The Characteristics of Binary Spike-Time-Dependent Plasticity in HfO2-Based RRAM and Applications for Pattern Recognition 期刊论文
NANOSCALE RESEARCH LETTERS, 2017
Zhou, Zheng; Liu, Chen; Shen, Wensheng; Dong, Zhen; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng
收藏  |  浏览/下载：6/0  |  提交时间：2017/12/03
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness 期刊论文
IEICE TRANSACTIONS ON ELECTRONICS, 2017
Wang, Yuan; Lu, Guangyi; Wang, Yize; Zhang, Xing
收藏  |  浏览/下载：3/0  |  提交时间：2017/12/03
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology 期刊论文
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 卷号: Vol.25 No.6, 页码: 1978-1982
作者:  Liang,Huaguo;  Xu,Xiumin;  Yi,Maoxiang;  Yan,Aibin;  Ouyang,Yiming
收藏  |  浏览/下载：3/0  |  提交时间：2019/04/22
A transient pulse dually filterable and online self-recoverable latch 期刊论文
IEICE ELECTRONICS EXPRESS, 2017, 卷号: Vol.14 No.2
作者:  Liang,Huaguo;  Lu,Yingchun;  Yan,Aibin;  Huang,Zhengfeng
收藏  |  浏览/下载：5/0  |  提交时间：2019/04/22
Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS 期刊论文
Microelectronics Journal, 2017, 卷号: Vol.61, 页码: 43-50
作者:  Fang,Xiangsheng;  Deng,Honghui;  Yan,Aibin;  Ouyang,Yiming;  Huang,Zhengfeng
收藏  |  浏览/下载：10/0  |  提交时间：2019/04/22
HLDTL: High-performance, low-cost, and double node upset tolerant latch design 期刊论文
Proceedings of the IEEE VLSI Test Symposium, 2017
作者:  Liang,Huaguo;  Yi,Maoxiang;  Cui,Jie;  Yan,Aibin;  Huang,Zhengfeng
收藏  |  浏览/下载：12/0  |  提交时间：2019/04/22

©版权所有 ©2017 CSpace - Powered by CSpace