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	Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology
	Liang,Huaguo; Xu,Xiumin; Yi,Maoxiang; Yan,Aibin; Ouyang,Yiming; Huang,Zhengfeng
刊名	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
	2017
卷号	Vol.25 No.6页码:1978-1982
关键词	HIGH-PERFORMANCE TOLERANT LATCH SEU COST
ISSN号	1063-8210;1557-9999
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2160022
专题	安徽大学
作者单位	1.Hefei Univ Technol, Sch Comp & Informat, Hefei 230009, Peoples R China 2.Anhui Univ, Sch Comp Sci & Technol, Hefei 230601, Peoples R China 3.Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Peoples R China
推荐引用方式 GB/T 7714	Liang,Huaguo,Xu,Xiumin,Yi,Maoxiang,et al. Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2017,Vol.25 No.6:1978-1982.
APA	Liang,Huaguo,Xu,Xiumin,Yi,Maoxiang,Yan,Aibin,Ouyang,Yiming,&Huang,Zhengfeng.(2017).Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol.25 No.6,1978-1982.
MLA	Liang,Huaguo,et al."Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology".IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol.25 No.6(2017):1978-1982.

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