CORC

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A JTAG-based configuration circuit applied in SerDes chip 其他
2011-01-01
Jiang, Xun; Cui, Xiaoxin; Yu, Dunshan
收藏  |  浏览/下载:3/0  |  提交时间:2015/11/10
A wide lock-range, low jitter phase-locked loop for multi-standard SerDes application 其他
2011-01-01
Liu, Shaolong; Wang, Hui; Cheng, Yuhua
收藏  |  浏览/下载:3/0  |  提交时间:2015/11/13
A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes 其他
2010-01-01
Zhihui, Zhao; Yuan, Wang; Junlei, Zhao; Hailing, Yang; Song, Jia
收藏  |  浏览/下载:4/0  |  提交时间:2015/11/13
A low power quad phase-locked loop for multiple SerDes standards 其他
2010-01-01
Meng, Qingrui; Wang, Hui; Cheng, Yuhua
收藏  |  浏览/下载:2/0  |  提交时间:2015/11/13
A low jitter 2.125GHz serial link for optical transmission 其他
2010-01-01
Hou, Zhongyuan; Liu, Junhua; Yang, Fan; Zhang, Xin
收藏  |  浏览/下载:4/0  |  提交时间:2015/11/13


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