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	A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes
	Zhihui, Zhao ; Yuan, Wang ; Junlei, Zhao ; Hailing, Yang ; Song, Jia
	2010
英文摘要	This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to lessen the problems in routing high speed clocks and reduce power. An improved half-rate bang-bang phase detector is presented to assure the stability of the system. Moreover, the paper proposes a simplified control scheme for the phase interpolator to further reduce power and cost. The CDR takes an area of less than 0.05mm2, and post simulation shows that the CDR has a RMS jitter of UIpp/32 (11.4ps@3.125GBaud) and consumes 9.5mW at 3.125GBaud. ? 2010 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/EDSSC.2010.5713726
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295489]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhihui, Zhao,Yuan, Wang,Junlei, Zhao,et al. A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes. 2010-01-01.

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