Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA

doi:10.1109/TCAD.2021.3082868

	Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA
	Li, Gang 1,5; Liu, Zejian 4,5; Li, Fanrong 4,5; Cheng, Jian 2,3,5
刊名	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
	2022-05-01
卷号	41 期号:5 页码:1436-1447
关键词	Convolution Field programmable gate arrays System-on-chip Task analysis Random access memory Tensors Memory management Block convolution convolutional neural network (CNN) accelerator field-programmable gate array (FPGA) memory efficient off-chip transfer
ISSN号	0278-0070
DOI	10.1109/TCAD.2021.3082868
通讯作者	Cheng, Jian(jcheng@nlpr.ia.ac.cn)
英文摘要	Deep convolutional neural networks have achieved remarkable progress in recent years. However, the large volume of intermediate results generated during inference poses a significant challenge to the accelerator design for resource-constrained field-programmable gate array (FPGA). Due to the limited on-chip storage, partial results of intermediate layers are frequently transferred back and forth between on-chip memory and off-chip DRAM, leading to a nonnegligible increase in latency and energy consumption. In this article, we propose block convolution, a hardware-friendly, simple, yet efficient convolution operation that can completely avoid the off-chip transfer of intermediate feature maps at runtime. The fundamental idea of block convolution is to eliminate the dependency of feature map tiles in the spatial dimension when spatial tiling is used, which is realized by splitting a feature map into independent blocks so that convolution can be performed separately on individual blocks. We conduct extensive experiments to demonstrate the efficacy of the proposed block convolution on both the algorithm side and the hardware side. Specifically, we evaluate block convolution on: 1) VGG-16, ResNet-18, ResNet-50, and MobileNet-V1 for the ImageNet classification task; 2) SSD and FPN for the COCO object detection task; and 3) VDSR for the Set5 single-image superresolution task. Experimental results demonstrate that comparable or higher accuracy can be achieved with block convolution. We also showcase two CNN accelerators via algorithm/hardware co-design based on block convolution on memory-limited FPGAs, and evaluation shows that both accelerators substantially outperform the baseline without off-chip transfer of intermediate feature maps.
资助项目	National Natural Science Foundation of China[61972396] ; National Key Research and Development Program of China[2020AAA0103402] ; Strategic Priority Research Program of Chinese Academy of Sciences[XDA27040300] ; Strategic Priority Research Program of Chinese Academy of Sciences[XDB32050200]
WOS研究方向	Computer Science ; Engineering
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000784196800022
资助机构	National Natural Science Foundation of China ; National Key Research and Development Program of China ; Strategic Priority Research Program of Chinese Academy of Sciences
内容类型	期刊论文
源URL	[http://ir.ia.ac.cn/handle/173211/48338]
专题	类脑芯片与系统研究
通讯作者	Cheng, Jian
作者单位	1.Univ Chinese Acad Sci, Sch Artificial Intelligence, Beijing 100049, Peoples R China 2.Chinese Acad Sci, Ctr Excellence Brain Sci & Intelligence Technol, Beijing 100190, Peoples R China 3.Univ Chinese Acad Sci, Beijing 100049, Peoples R China 4.Univ Chinese Acad Sci, Sch Future Technol, Beijing 100049, Peoples R China 5.Chinese Acad Sci, Inst Automat, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Li, Gang,Liu, Zejian,Li, Fanrong,et al. Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2022,41(5):1436-1447.
APA	Li, Gang,Liu, Zejian,Li, Fanrong,&Cheng, Jian.(2022).Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,41(5),1436-1447.
MLA	Li, Gang,et al."Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 41.5(2022):1436-1447.