QQ客服 官方微博 反馈留言

浏览/检索结果: 共11条，第1-10条 帮助 限定条件 专题：武汉轻工大学    第一署名单位    第一作者单位    通讯作者单位     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 Molecular characterization of multidrug-resistant Mycobacterium tuberculosis isolated from South-central in China 期刊论文 The Journal of Antibiotics, 2013, 卷号: 67, 期号: 4, 页码: 291-297 作者:  Yu, Xiao-li;  Wen, Zi-lu;  Chen, Gao-zhan;  Li, Rui;  Ding, Bing-bing 收藏  |  浏览/下载：1/0  |  提交时间：2019/12/27 Beijing genotypes  M. tuberculosis  extensively drug resistance  multidrug-resistance  mutation   Design of VSS software configuration management database for WEB application project 会议论文 2009 Pacific-Asia Conference on Circuits, Communications and System, PACCS 2009, Chengdu, China, May 16, 2009 - May 17, 2009 作者:  Ding YueHua*;  Xiang RiHua;  Yi Kui 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/27 SCM  Web Development  VSS   32-bit RISC CPU Based on MIPS Instruction Fetch Module Design 会议论文 1st IITA International Joint Conference on Artificial Intelligence, Hainan Isl, PEOPLES R CHINA, APR 25-MAY 26, 2009 作者:  Yi, Kui*;  Ding, Yue-Hua 收藏  |  浏览/下载：2/0  |  提交时间：2019/12/27 MIPS  Data Flow  Data Path  Pipeline   32-bit RISC CPU based on MIPS instruction decoder module design 会议论文 2009 2nd Pacific-Asia Conference on Web Mining and Web-Based Application, WMWA 2009, Wuhan, China, June 6, 2009 - June 7, 2009 作者:  Yi, Kui*;  Ding, Yue-Hua 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/27 MIPS  Data Flow  Data Path  Pipeline   32 bit Multiplication and Division ALU Design Based on RISC Structure 会议论文 1st IITA International Joint Conference on Artificial Intelligence, Hainan Isl, PEOPLES R CHINA, APR 25-MAY 26, 2009 作者:  Yi, Kui*;  Ding, Yue-Hua 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/27 pipelining  IEEE-754 Standard  VHDL   32-bit RISC CPU based on MIPS instruction decoder module design 会议论文 2009 2nd Pacific-Asia Conference on Web Mining and Web-Based Application, WMWA 2009, Wuhan, China, June 6, 2009 - June 7, 2009 作者:  Yi, Kui*;  Ding, Yue-Hua 收藏  |  浏览/下载：1/0  |  提交时间：2019/12/27 MIPS  Data Flow  Data Path  Pipeline   Instruction Fetch Module Design of 32-bit RISC CPU Based on MIPS 会议论文 International Symposium on Distributed Computing and Applications to Business, Engineering and Science, Dalian, PEOPLES R CHINA, JUL 27-31, 2008 作者:  Ding, Yuehua*;  Yi, Kui;  Sun, Ping 收藏  |  浏览/下载：4/0  |  提交时间：2019/12/27 MIPS  Data Flow  Data Path  Pipeline   General Register Design 会议论文 International Symposium on Distributed Computing and Applications to Business, Engineering and Science, Dalian, PEOPLES R CHINA, JUL 27-31, 2008 作者:  Yi, Kui*;  Ding, Yuehua;  Du, Xin 收藏  |  浏览/下载：2/0  |  提交时间：2019/12/27 MIPS  RISC  VHDL  FPGA  CPU  General Register   32 bit floating-point addition and subtraction ALU design 会议论文 International Symposium on Distributed Computing and Applications to Business, Engineering and Science, Yichang, PEOPLES R CHINA, AUG 14-17, 2007 作者:  Yi, Kui*;  Xiong, Pin;  Ding, Yuehua 收藏  |  浏览/下载：2/0  |  提交时间：2019/12/27 pipelining  IEEE-754 standard  VHDL   32 bit multiplication and division ALU design based on RISC structure 会议论文 International Symposium on Distributed Computing and Applications to Business, Engineering and Science, Yichang, PEOPLES R CHINA, AUG 14-17, 2007 作者:  Ding, Yuehua*;  Yi, Kui 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/27 pipelining  IEEE-754 standard  VHDL