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浏览/检索结果: 共5条，第1-5条 帮助 限定条件 内容类型：会议论文     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 A method of converting CameraLink into HDMI based on FPGA 会议论文 Shanghai, China, 2018-05-08 作者:  Du, Xingqian;  Zhang, Haifeng;  Feng, Jia;  Xie, Qingsheng 收藏  |  浏览/下载：30/0  |  提交时间：2018/09/20 Cameralink  Hdmi  Fpga  Color Space   Effect of water-leaching on the fine particle formation during biomass combustion 会议论文 作者:  Wang, Xuebin;  Adeosun, Adewale;  Hu, Zhongfa;  Li, Tianxiang;  Tan, Houzhang 收藏  |  浏览/下载：8/0  |  提交时间：2019/11/26 Electrical low-pressure impactor  Energy dispersive X ray spectroscopy  Entrained Flow Reactor  Fine particles  High speed video cameras  Low pressure impactor  Thermogravimetric analyzers  Water leaching   Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China Sun H.; Cai R.; Wang Y. 收藏  |  浏览/下载：25/0  |  提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera  the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition  these functions that adjustments of exposure beginning time  integral time  AOI (Area of Interest) output and so on  are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip)  and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate  low power  intelligent and miniaturization digital video camera.   Real-time quality control on a smart camera (EI CONFERENCE) 会议论文 ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China Xiao C.; Zhou H.; Li G.; Hao Z. 收藏  |  浏览/下载：18/0  |  提交时间：2013/03/25 A smart camera is composed of a video sensing  high-level video processing  communication and other affiliations within a single device. Such cameras are very important devices in quality control systems. This paper presents a prototyping development of a smart camera for quality control. The smart camera is divided to four parts: a CMOS sensor  a digital signal processor (DSP)  a CPLD and a display device. In order to improving the processing speed  low-level and high-level video processing algorithms are discussed to the embedded DSP-based platforms. The algorithms can quickly and automatic detect productions' quality defaults. All algorithms are tested under a Matlab-based prototyping implementation and migrated to the smart camera. The smart camera prototype automatic processes the video data and streams the results of the video data to the display devices and control devices. Control signals are send to produce-line to adjust the producing state within the required real-time constrains.   Key techniques on design of laser high-speed video system for recording metal transfer in arc welding (EI收录) 会议论文 2007 8th International Conference on Electronic Measurement and Instruments, ICEMI, Xian, China, August 16, 2007 - August 18, 2007 作者:  Wen, Yuan-Mei[1,2];  Huang, Shi-Sheng[1];  Xue, Jia-Xiang[1];  Liu, Xiao[1] 收藏  |  浏览/下载：3/0  |  提交时间：2019/04/17 Cavity resonators  Computer networks  Electric arc welding  High speed cameras  Lasers  Mass transfer  Mass transportation  Smelting  Speed  Welding