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浏览/检索结果: 共9条，第1-9条 帮助 限定条件 发表日期：2015     已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择作者升序作者降序题名升序题名降序发表日期升序发表日期降序提交时间升序提交时间降序 A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文 IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 8, 页码: 6 作者:  Liu, Bosheng l;  Wang, Ying;  You, Zhiqiang;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：15/0  |  提交时间：2019/12/13 full adder  memristor ratioed logic (MRL) gate   Simplified carry save adder-based array multiplier scheme and circuits design 期刊论文 INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2015 Jia, Song; Lyu, Shigong; Li, Xiayu; Liu, Li; He, Yandong 收藏  |  浏览/下载：2/0  |  提交时间：2017/12/03 array multiplier  carry save adders  partial products  high speed  low power  PERFORMANCE LOW-POWER  CMOS   Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 卷号: 62, 页码: 1757-1765 作者:  Deng, Erya;  Zhang, Yue;  Kang, Wang;  Dieny, Bernard;  Klein, Jacques-Olivier 收藏  |  浏览/下载：4/0  |  提交时间：2020/01/06 3-D integration  8-bit flip-flop  8-bit full-adder  full non-volatility  STT-MTJ  synchronous   High-Frequency Low-Power Magnetic Full-Adder Based on Magnetic Tunnel Junction With Spin-Hall Assistance 会议论文 IEEE International Magnetics Conference (Intermag), Beijing, PEOPLES R CHINA, 2015-11-01 作者:  Deng, Erya;  Wang, Zhaohao;  Klein, Jacques-Olivier;  Prenat, Guillaume;  Dieny, Bernard 收藏  |  浏览/下载：5/0  |  提交时间：2020/01/06 Hybrid logic-in-memory  magnetic full-adder (MFA)  magnetic tunnel junction (MTJ)  spin-Hall effect (SHE)  spin-transfer torque (STT)   Robust Magnetic Full-Adder with Voltage Sensing 2T/2MTJ Cell 会议论文 PROCEEDINGS OF THE 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 15), 2015-01-01 作者:  Deng, Erya;  Wang, You;  Wang, Zhaohao;  Klein, Jacques-Olivier;  Dieny, Bernard 收藏  |  浏览/下载：3/0  |  提交时间：2020/01/06 magnetic tunnel junction  3-D integration  magnetic full-adder  high reliability  voltage sensing   Full-adder Circuit Design Based on All-spin Logic Device 会议论文 PROCEEDINGS OF THE 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 15), 2015-01-01 作者:  An, Qi;  Su, Li;  Klein, Jacques-Olivier;  Le Beux, Sebastien;  O'Connor, Ian 收藏  |  浏览/下载：5/0  |  提交时间：2020/01/06 all spin logic  design method  full-adder  spintronics   High-Frequency Low-Power Magnetic Full-Adder Based on Magnetic Tunnel Junction With Spin-Hall Assistance 期刊论文 IEEE TRANSACTIONS ON MAGNETICS, 2015, 卷号: 51 作者:  Deng, Erya;  Wang, Zhaohao;  Klein, Jacques-Olivier;  Prenat, Guillaume;  Dieny, Bernard 收藏  |  浏览/下载：11/0  |  提交时间：2020/01/06 Hybrid logic-in-memory  magnetic full-adder (MFA)  magnetic tunnel junction (MTJ)  spin-Hall effect (SHE)  spin-transfer torque (STT)   A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文 IEICE Electron. Express, 2015, 卷号: Vol.12 No.0 - 收藏  |  浏览/下载：2/0  |  提交时间：2019/12/31 full  adder  memristor  ratioed  logic  (MRL)  gate   A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文 IEICE ELECTRONICS EXPRESS, 2015, 卷号: Vol.12 No.8 作者:  Liu, BS;  Wang, Y;  You, ZQ;  Han, YH;  Li, XW 收藏  |  浏览/下载：3/0  |  提交时间：2019/12/31 full  adder  memristor  ratioed  logic  (MRL)  gate