High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime | |
Yang, Yumei1; Lou, Haijun2,3; Lin, Xinnan3 | |
刊名 | IEEE TRANSACTIONS ON ELECTRON DEVICES |
2018-12 | |
卷号 | 65期号:12页码:5282-5288 |
关键词 | High-k spacer junctionless nonequilibrium Green function (NEGF) quantum simulator |
ISSN号 | 0018-9383 |
DOI | 10.1109/TED.2018.2873717 |
英文摘要 | In this paper, we investigate the impact of spacer dielectrics on the ultrascaled silicon gate-all-around junctionless transistor in the ballistic regime based on the in-house 3-D quantum simulator that self-consistently solves mode-space nonequilibrium Green function formalism and Poisson's equation. Then, the impact of device parameters, such as lengths of source/drain region and channel, channel width, and nanowire direction, on the static performance is also discussed in detail. An available range of spacer dielectric constant is further selected. Results show that the high-k spacer introduced in the ultrascaled junctionless transistor can effectively enhance the direct-current performance of the device and suppress the variation of drain current and subthreshold characteristics induced by the aforementioned device parameters. It will be a great benefit for the junctionless device with a gate-all-around structure as the scaling continues to approach the end of MOSFETs. |
资助项目 | Shenzhen Key Laboratory Project[ZDSYS20170303140513705] |
WOS研究方向 | Engineering ; Physics |
语种 | 英语 |
出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
WOS记录号 | WOS:000451255200003 |
状态 | 已发表 |
内容类型 | 期刊论文 |
源URL | [http://119.78.100.223/handle/2XXMBERH/32319] |
专题 | 理学院 |
通讯作者 | Lou, Haijun |
作者单位 | 1.Lanzhou Univ Technol, Sch Sci, Lanzhou 730050, Gansu, Peoples R China 2.Zhejiang Univ, Inst Adv Technol, Hangzhou 310058, Zhejiang, Peoples R China 3.Peking Univ, Shenzhen Grad Sch, Sch Elect & Comp Engn, Shenzhen Key Lab Adv Electron Device & Integrat, Shenzhen 518055, Peoples R China |
推荐引用方式 GB/T 7714 | Yang, Yumei,Lou, Haijun,Lin, Xinnan. High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES,2018,65(12):5282-5288. |
APA | Yang, Yumei,Lou, Haijun,&Lin, Xinnan.(2018).High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime.IEEE TRANSACTIONS ON ELECTRON DEVICES,65(12),5282-5288. |
MLA | Yang, Yumei,et al."High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime".IEEE TRANSACTIONS ON ELECTRON DEVICES 65.12(2018):5282-5288. |
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