Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint

doi:10.1002/advs.201901224

CORC > 宁波材料技术与工程研究所 > 中国科学院宁波材料技术与工程研究所 > 2020专题

	Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint
	Qi, Shaocheng ; Cunha, Joao ; Guo, Tian-Long ; Chen, Peiqin ; Zaccaria, Remo Proietti ; Dai, Mingzhi
刊名	ADVANCED SCIENCE
	2020
卷号	7 期号:6
关键词	THIN-FILM TRANSISTORS INTEGRATED-CIRCUITS MEMORY
DOI	10.1002/advs.201901224
英文摘要	Logic functions are the key backbone in electronic circuits for computing applications. Complementary metal-oxide-semiconductor (CMOS) logic gates, with both n-type and p-type channel transistors, have been to date the dominant building blocks of logic circuitry as they carry obvious advantages over other technologies. Important physical limits are however starting to arise, as the transistor-processing technology has begun to meet scaling-down difficulties. To address this issue, there is the crucial need for a next-generation electronics era based on new concepts and designs. In this respect, a single-type channel multigate MOS transistor (SMG-MOS) is introduced holding the two important aspects of processing adaptability and low static dissipation of CMOS. Furthermore, the SMG-MOS approach strongly reduces the footprint down to 40% or even less area needed for current CMOS logic function in the same processing technology node. Logic NAND, NOT, AND, NOR, and OR gates, which typically require a large number of CMOS transistors, can be realized by a single SMG-MOS transistor. Two functional examples of SMG-MOS are reported here with their analysis based both on simulations and experiments. The results strongly suggest that SMG-MOS can represent a facile approach to scale down complex integrated circuits, enabling design flexibility and production rates ramp-up.
学科主题	Chemistry ; Science & Technology - Other Topics ; Materials Science
内容类型	期刊论文
源URL	[http://ir.nimte.ac.cn/handle/174433/20140]
专题	2020专题
作者单位	1.Dai, MZ (corresponding author), Chinese Acad Sci, Ningbo Inst Mat Technol & Engn, Ningbo 315201, Peoples R China. 2.Zaccaria, RP (corresponding author), Chinese Acad Sci, Ningbo Inst Mat Technol & Engn, Cixi Inst Biomed Engn, Ningbo 315201, Peoples R China. 3.Zaccaria, RP (corresponding author), Ist Italiano Tecnol, Via Morego 30, I-16163 Genoa, Italy.
推荐引用方式 GB/T 7714	Qi, Shaocheng,Cunha, Joao,Guo, Tian-Long,et al. Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint[J]. ADVANCED SCIENCE,2020,7(6).
APA	Qi, Shaocheng,Cunha, Joao,Guo, Tian-Long,Chen, Peiqin,Zaccaria, Remo Proietti,&Dai, Mingzhi.(2020).Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint.ADVANCED SCIENCE,7(6).
MLA	Qi, Shaocheng,et al."Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint".ADVANCED SCIENCE 7.6(2020).