A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification

doi:10.3390/s20174715

CORC > 计算技术研究所 > 中国科学院计算技术研究所 > 中国科学院计算技术研究所期刊论文 > 英文

	A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification
	He, Wei 1; Huang, Jinguo 1; Wang, Tengxiao 1; Lin, Yingcheng 1; He, Junxian 1; Zhou, Xichuan 1,2; Li, Ping 1,2; Wang, Ying 3; Wu, Nanjian 4; Shi, Cong 1,2
刊名	SENSORS
	2020-09-01
卷号	20 期号:17 页码:18
关键词	address-event representation (AER) Random Ferns object classification neuromorphic hardware online learning on-chip learning
DOI	10.3390/s20174715
英文摘要	This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed system executes a lightweight statistic algorithm based on simple binary features extracted from AER streams and a Random Ferns classifier to classify these features. The proposed system's characteristics of multi-level pipelines and parallel processing circuits achieves a high throughput up to 1 spike event per clock cycle for AER data processing. Thanks to the nature of the lightweight algorithm, our hardware system is realized in a low-cost memory-centric paradigm. In addition, the system is capable of on-chip online learning to flexibly adapt to different in-situ application scenarios. The extra overheads for on-chip learning in terms of time and resource consumption are quite low, as the training procedure of the Random Ferns is quite simple, requiring few auxiliary learning circuits. An FPGA prototype of the proposed VLSI system was implemented with 9.5 similar to 96.7% memory consumption and <11% computational and logic resources on a Xilinx Zynq-7045 chip platform. It was running at a clock frequency of 100 MHz and achieved a peak processing throughput up to 100 Meps (Mega events per second), with an estimated power consumption of 690 mW leading to a high energy efficiency of 145 Meps/W or 145 event/mu J. We tested the prototype system on MNIST-DVS, Poker-DVS, and Posture-DVS datasets, and obtained classification accuracies of 77.9%, 99.4% and 99.3%, respectively. Compared to prior works, our VLSI system achieves higher processing speeds, higher computing efficiency, comparable accuracy, and lower resource costs.
资助项目	Key Project of Chongqing Science and Technology Foundation[cstc2019jcyj-zdxmX0017] ; Chongqing Talents Plan for Yong Talents[CQYC201905015] ; Open Research Funding from the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences[CARCH201908]
WOS研究方向	Chemistry ; Engineering ; Instruments & Instrumentation
语种	英语
出版者	MDPI
WOS记录号	WOS:000569758500001
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/15544]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Shi, Cong
作者单位	1.Chongqing Univ, Sch Microelect & Commun Engn, Chongqing 400044, Peoples R China 2.Chongqing Univ, Minist Educ, Key Lab Dependable Serv Comp Cyber Phys Soc, Chongqing 400044, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 4.Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China
推荐引用方式 GB/T 7714	He, Wei,Huang, Jinguo,Wang, Tengxiao,et al. A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification[J]. SENSORS,2020,20(17):18.
APA	He, Wei.,Huang, Jinguo.,Wang, Tengxiao.,Lin, Yingcheng.,He, Junxian.,...&Shi, Cong.(2020).A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification.SENSORS,20(17),18.
MLA	He, Wei,et al."A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification".SENSORS 20.17(2020):18.