Optoelectronic integrated circuit | |
SASAKI GORO | |
1989-11-30 | |
著作权人 | SUMITOMO ELECTRIC IND LTD |
专利号 | JP1989296663A |
国家 | 日本 |
文献子类 | 发明申请 |
其他题名 | Optoelectronic integrated circuit |
英文摘要 | PURPOSE:To contrive a flattening of the surface of an optoelectronic integrated circuit device by a method wherein a semi-insulative InP layer is selectively formed on an InP substrate in such a way as to bury an optical element formed on the substrate in the InP layer and an electronic element is formed on this semi-insulative InP layer. CONSTITUTION:A semiconductor layer 2, which uses an epitaxial layer 10 laminated with a dissimilar material as an operating layer, is formed on an InP substrate 1 and a semi-insulative InP layer 3 is selectively formed on the substrate 1 in such a way as to bury the layer 2 in its periphery. Moreover, the thickness of the layer 3 is formed in the same thickness as that of the layer 2 and a field-effect transistor 4 is formed on the surface of the layer 3. Moreover, the transistor 4 is one that uses an epitaxial layer 5 as an operating layer and a gate electrode 6 is formed on the layer 5. Thereby, the surface of the semi-insulative InP layer, on which an electronic element is formed, and the upper end part of the optical element are formed in the almost same height and the surface of an optoelectronic integrated circuit device is flattened. |
公开日期 | 1989-11-30 |
申请日期 | 1988-05-25 |
状态 | 失效 |
内容类型 | 专利 |
源URL | [http://ir.opt.ac.cn/handle/181661/89744] |
专题 | 半导体激光器专利数据库 |
作者单位 | SUMITOMO ELECTRIC IND LTD |
推荐引用方式 GB/T 7714 | SASAKI GORO. Optoelectronic integrated circuit. JP1989296663A. 1989-11-30. |
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