A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

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	A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit
	Kuang, XF ; Wu, NJ ; Shou, GL
	2006
会议名称	international conference on solid state devices and materials (
会议日期	sep 13-15, 2005
会议地点	kobe, japan
关键词	lock-in speed
页码	45 (4b): 3290-3294
通讯作者	kuang, xf, chinese acad sci, inst semicond, state key lab superlattices & microstruct, pob 912, beijing 100083, peoples r china.
中文摘要	this paper proposes a novel, fast lock-in, phase-locked loop (pll) frequency synthesizer. the synthesizer includes a novel mixed-signal voltage-controlled oscillator (vco) with a direct frequency presetting circuit. the frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the vco. we fully integrated the synthesizer in standard 0.35 mu m, 3.3 v complementary metal-oxide-semiconductors (cmos) process. the entire chip area is only 0.4 mm(2). the measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. the measured phase noise of the synthesizer is -85 dbc/hz at 10 khz offset. the synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. the synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.
英文摘要	this paper proposes a novel, fast lock-in, phase-locked loop (pll) frequency synthesizer. the synthesizer includes a novel mixed-signal voltage-controlled oscillator (vco) with a direct frequency presetting circuit. the frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the vco. we fully integrated the synthesizer in standard 0.35 mu m, 3.3 v complementary metal-oxide-semiconductors (cmos) process. the entire chip area is only 0.4 mm(2). the measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. the measured phase noise of the synthesizer is -85 dbc/hz at 10 khz offset. the synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. the synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.; zhangdi于2010-03-29批量导入; zhangdi于2010-03-29批量导入; japan soc appl phys & tech.; ieee elect devices soc.; chinese acad sci, inst semicond, state key lab superlattices & microstruct, beijing 100083, peoples r china; liuhewantong microelect ltd, beijing 100085, peoples r china
收录类别	其他
会议主办者	japan soc appl phys & tech.; ieee elect devices soc.
会议录	japanese journal of applied physics part 1-regular papers brief communications & review papers
会议录出版者	inst pure applied physics ; 5f yushima bldg, 2-31-22 yushima, bunkyo-ku, tokyo, 113-0034, japan
会议录出版地	5f yushima bldg, 2-31-22 yushima, bunkyo-ku, tokyo, 113-0034, japan
学科主题	半导体物理
语种	英语
ISSN号	0021-4922
内容类型	会议论文
源URL	[http://ir.semi.ac.cn/handle/172111/10024]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Kuang, XF,Wu, NJ,Shou, GL. A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit[C]. 见:international conference on solid state devices and materials (. kobe, japan. sep 13-15, 2005.