Design and Verification of the Programming Circuit in an Application-Specific FPGA

CORC > 半导体研究所 > 中国科学院半导体研究所 > 中国科学院半导体研究所（2009年前）

	Design and Verification of the Programming Circuit in an Application-Specific FPGA
	Yang ZC ; Chen SL ; Liu ZL
	2008
会议名称	9th international conference on solid-state and integrated-circuit technology
会议日期	oct 20-23, 2008
会议地点	beijing, peoples r china
页码	vols 1-4: 2039-2042
通讯作者	yang, zc, chinese acad sci, inst semicond, beijing 100083, peoples r china.
中文摘要	in this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific fpgas that share a common architecture. each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. the parametrized design methodology is presented here to achieve this goal. even though our focus is on the programming circuitry that provides the interface between the fpga core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the fpga family. the method presented here covers the generation of the design rtl files and the support files for synthesis, place-and-route layout and simulations. the proposed method is proven to work smoothly within the complete chip design methodology. we will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. different package options and different programming modes are included in the description of the design. the circuit design implementation is based on smic 0.13-micron cmos technology.
英文摘要	in this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific fpgas that share a common architecture. each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. the parametrized design methodology is presented here to achieve this goal. even though our focus is on the programming circuitry that provides the interface between the fpga core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the fpga family. the method presented here covers the generation of the design rtl files and the support files for synthesis, place-and-route layout and simulations. the proposed method is proven to work smoothly within the complete chip design methodology. we will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. different package options and different programming modes are included in the description of the design. the circuit design implementation is based on smic 0.13-micron cmos technology.; zhangdi于2010-03-09批量导入; zhangdi于2010-03-09批量导入; ieee beijing sect.; chinese inst elect.; ieee electron devices soc.; ieee eds beijing chapter.; ieee solid state circuits soc.; ieee circuites & syst soc.; ieee hong kong eds, sscs chapter.; ieee sscs beijing chapter.; japan soc appl phys.; elect div ieee.; ursi commiss d.; inst elect engineers korea.; assoc asia pacific phys soc.; peking univ, ieee eds student chapter.; [yang, zhichao; chen, stanley l.; liu, zhongli] chinese acad sci, inst semicond, beijing 100083, peoples r china
收录类别	其他
会议主办者	ieee beijing sect.; chinese inst elect.; ieee electron devices soc.; ieee eds beijing chapter.; ieee solid state circuits soc.; ieee circuites & syst soc.; ieee hong kong eds, sscs chapter.; ieee sscs beijing chapter.; japan soc appl phys.; elect div ieee.; ursi commiss d.; inst elect engineers korea.; assoc asia pacific phys soc.; peking univ, ieee eds student chapter.
会议录	2008 9th international conference on solid-state and integrated-circuit technology
会议录出版者	ieee ; 345 e 47th st, new york, ny 10017 usa
会议录出版地	345 e 47th st, new york, ny 10017 usa
学科主题	微电子学
语种	英语
ISBN号	978-1-4244-2185-5
内容类型	会议论文
源URL	[http://ir.semi.ac.cn/handle/172111/8302]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Yang ZC,Chen SL,Liu ZL. Design and Verification of the Programming Circuit in an Application-Specific FPGA[C]. 见:9th international conference on solid-state and integrated-circuit technology. beijing, peoples r china. oct 20-23, 2008.