| Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices | |
| Zhang, Deming; Hou, Yanchun; Wang, Chengzhi; Chen, Jie; Zeng, Lang; Zhao, Weisheng | |
| 2015 | |
| 会议名称 | NANOARCH'18: PROCEEDINGS OF THE 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES |
| 会议日期 | 2015-01-01 |
| 关键词 | Sparse coding MTJ DWM neuromorphic computing hardware acceleration multiple conductance states ANN |
| 页码 | 79-85 |
| 收录类别 | CPCI-S |
| URL标识 | 查看原文 |
| WOS记录号 | WOS:000457790100015 |
| 内容类型 | 会议论文 |
| URI标识 | http://www.corc.org.cn/handle/1471x/6544833 |
| 专题 | 北京航空航天大学 |
| 推荐引用方式 GB/T 7714 | Zhang, Deming,Hou, Yanchun,Wang, Chengzhi,et al. Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices[C]. 见:NANOARCH'18: PROCEEDINGS OF THE 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES. 2015-01-01. |
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