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	A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy
	Chao YAN; Hongjun DAI; Tianzhou CHEN
刊名	IEICE transactions on information and systems
	2012
卷号	E95D期号:1页码:38-45
关键词	soft errors fault tolerance double execution instruction reuse buffer fast error correcting code
DOI	10.1587/transinf.E95.D.38
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/5217492
专题	山东大学
作者单位	1.Department of Computer Science and Technology, Shandong University, Jinan, China 2.Department of Computer Science and Technology, Sha
推荐引用方式 GB/T 7714	Chao YAN,Hongjun DAI,Tianzhou CHEN. A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy[J]. IEICE transactions on information and systems,2012,E95D(1):38-45.
APA	Chao YAN,Hongjun DAI,&Tianzhou CHEN.(2012).A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy.IEICE transactions on information and systems,E95D(1),38-45.
MLA	Chao YAN,et al."A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy".IEICE transactions on information and systems E95D.1(2012):38-45.

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