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	All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters
	Chen, Shuai; Wang, Luke; Zhang, Hong; Murugesu, Rosanah; Dunwell, Dustin; Carusone, Anthony Chan
刊名	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
	2017
卷号	25页码:2552-2560
关键词	finite-impulse response (FIR) filter analog-to-digital converter (ADC) All-digital calibration derivative timing mismatch time interleaving (TI)
ISSN号	1063-8210
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2948427
专题	西安交通大学
推荐引用方式 GB/T 7714	Chen, Shuai,Wang, Luke,Zhang, Hong,et al. All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017,25:2552-2560.
APA	Chen, Shuai,Wang, Luke,Zhang, Hong,Murugesu, Rosanah,Dunwell, Dustin,&Carusone, Anthony Chan.(2017).All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,25,2552-2560.
MLA	Chen, Shuai,et al."All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25(2017):2552-2560.

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