Chip Multithreaded Consistency Model | |
Dan-Dan Huan; Zhi-Min Tang; Zu-Song Li; Wei-Wu Hu | |
刊名 | Journal of Computer Science and Technology |
2008 | |
卷号 | 23期号:2页码:298 |
关键词 | Computer Architecture Godson-2 Multithreading Memory Consistency Model Event Ordering |
英文摘要 | Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and ensures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread. |
语种 | 英语 |
公开日期 | 2010-11-02 |
内容类型 | 期刊论文 |
源URL | [http://ictir.ict.ac.cn/handle/311040/814] |
专题 | 中国科学院计算技术研究所期刊论文_2008年英文 |
推荐引用方式 GB/T 7714 | Dan-Dan Huan,Zhi-Min Tang,Zu-Song Li,et al. Chip Multithreaded Consistency Model[J]. Journal of Computer Science and Technology,2008,23(2):298. |
APA | Dan-Dan Huan,Zhi-Min Tang,Zu-Song Li,&Wei-Wu Hu.(2008).Chip Multithreaded Consistency Model.Journal of Computer Science and Technology,23(2),298. |
MLA | Dan-Dan Huan,et al."Chip Multithreaded Consistency Model".Journal of Computer Science and Technology 23.2(2008):298. |
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