Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2(m))

doi:10.1109/TCSI.2018.2795380

CORC > 上海财经大学 > 上海财经大学

	Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2(m))
	Shao, Qiliang 1; Hu, Zhenji 2; Basha, Shaik Nazeem 1; Zhang, Zhiping 1; Wu, Zhiqiang 1; Lee, Chiou-Yng 3; Xie, Jiafeng 1
刊名	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
	2018-08
卷号	65 期号:8 页码:2455-2465
关键词	Computation-core finite field multiplication hybrid-size low register-complexity polynomial basis systolic structure unified structure
ISSN号	1549-8328
DOI	10.1109/TCSI.2018.2795380
英文摘要	Systolic finite field multiplier over GF(2(m)) based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over GF(2(m)). We have proposed a computation-core-based design strategy to obtain the desired low-complexity unified multiplier for both NIST pentanomials and trinomials. The proposed multiplier can swift between pentanomial-based and trinomial-based multipliers through a control signal. First of all, a novel strategy is briefly introduced to implement a certain matrix-vector multiplication, which can be packed as a standard computation core (or computation core like). Then, based on the computation-core concept, a novel unified multiplication algorithm is derived that it can realize both the pentanomial-based and trinomial-based multiplications. After that, an efficient systolic structure is presented that it can fully employ the introduced computation core. A detailed example of the proposed unified multiplier (for GF(2(163)) and GF(2(233))) is also presented. Both the theoretical and field-programmable gate array implementation results show that the proposed design has efficient performance in area-time-power complexities, e.g., the proposed design (the one performs GF(2(163)) and GF(2(233)) multiplications) is found to have at least 14.2% and 13.3% less area-delay product and power-delay product than the combination of the existing individual GF(2(163)) and GF(2(233)) multipliers (best among all competing designs), respectively. Because of its structural regularity and functional flexibility, the proposed unified multiplier can be used as an intellectual property core for various cryptosystems.
WOS研究方向	Engineering
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000437882000010
内容类型	期刊论文
源URL	[http://10.2.47.112/handle/2XS4QKH4/562]
专题	上海财经大学
通讯作者	Xie, Jiafeng
作者单位	1.Wright State Univ, Dept Elect Engn, Dayton, OH 45435 USA; 2.Shanghai Univ Finance & Econ, Sch Law, Shanghai 200433, Peoples R China; 3.Lunghwa Univ Sci & Technol, Dept Comp Informat & Network Engn, Taoyuan 33306, Taiwan
推荐引用方式 GB/T 7714	Shao, Qiliang,Hu, Zhenji,Basha, Shaik Nazeem,et al. Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2(m))[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2018,65(8):2455-2465.
APA	Shao, Qiliang.,Hu, Zhenji.,Basha, Shaik Nazeem.,Zhang, Zhiping.,Wu, Zhiqiang.,...&Xie, Jiafeng.(2018).Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2(m)).IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,65(8),2455-2465.
MLA	Shao, Qiliang,et al."Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2(m))".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 65.8(2018):2455-2465.