Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices | |
Chen, Shen-Li ; Yang, Chih-Hung ; Yen, Chih-Ying ; Chen, Kuei-Jyun ; Wu, Yi-Cih ; Lin, Jia-Ming | |
2016 | |
英文摘要 | The electrostatic-discharge (ESD) protection capability of HV nLDMOS devices with the source-side engineering by a TSMC 0.25��m 60-V is investigated in this paper. It can be found that a pure nLDMOS device has a poor anti-ESD ability (It2 = 1.833A). At the same time, if an nLDMOS was embedded with an SCR npn-(pnp-) arranged type in the drain-side, the corresponding secondary breakdown-current values are promoted 19.4% (24.8%) as comparing with a traditional nLDMOS. Furthermore, if the source discrete methodology is applied for the nLDMOS-embedded SCR npn-(pnp-) arranged type, the maximum secondary breakdown current value are promoted 24.1% (>281.9%). Finally, it can be concluded that a discrete distribution in the source region of a pure nLDMOS will upgrade the anti-ESD capability effectively, and it is especially for the nLDMOS-SCR pnp-arranges type. ? 2016 IEEE.; EI |
语种 | 英语 |
出处 | 3rd IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2016 |
DOI标识 | 10.1109/ICCE-TW.2016.7521041 |
内容类型 | 其他 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/449325] |
专题 | 软件与微电子学院 |
推荐引用方式 GB/T 7714 | Chen, Shen-Li,Yang, Chih-Hung,Yen, Chih-Ying,et al. Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices. 2016-01-01. |
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