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	A 16GS/s 6-bit Current-Steering DAC with TI topology in 40nm CMOS; A 16GS/s 6-bit Current-Steering DAC with TI topology in 40nm CMOS
	Bao Li ; Long Zhao ; Chenxi Deng ; Yuhua Cheng
	2016
关键词	topology segmented SFDR steering analog converter programmed clock dissipation decoder topology segmented SFDR steering analog converter programmed clock dissipation decoder
英文摘要	A 6-bit pseudo segmented current-steering digital-to-analog converter(DAC) designed in 40 nm low-leakage(LL) CMOS process is presented. The DAC employs 4X time-interleaved(TI) topology which enables sampling rates up to 16GS/s with relatively low clock frequency. A design-for-test on-chip memory with 6bits1-k bytes/bit is programmed with strictly costumed data sequence and read out at 1Gb/s rate, independently. The DAC achieves 5.54-bit effective number of bit(ENOB) and 42.33 d Bc spurious free dynamic range(SFDR) at Nyquist frequency, respectively. Simulation results show the DAC consumes less than 230 mW power dissipation from 1.1V supply.; A 6-bit pseudo segmented current-steering digital-to-analog converter(DAC) designed in 40 nm low-leakage(LL) CMOS process is presented. The DAC employs 4X time-interleaved(TI) topology which enables sampling rates up to 16GS/s with relatively low clock frequency. A design-for-test on-chip memory with 6bits1-k bytes/bit is programmed with strictly costumed data sequence and read out at 1Gb/s rate, independently. The DAC achieves 5.54-bit effective number of bit(ENOB) and 42.33 d Bc spurious free dynamic ran; IEEE Beijing Section; 3
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/479818]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Bao Li,Long Zhao,Chenxi Deng,et al. A 16GS/s 6-bit Current-Steering DAC with TI topology in 40nm CMOS, A 16GS/s 6-bit Current-Steering DAC with TI topology in 40nm CMOS. 2016-01-01.

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