Design Considerations of SAR ADCs in CMOS Technology for High Speed Circuit Applications with a Time-interleaved Architecture; Design Considerations of SAR ADCs in CMOS Technology for High Speed Circuit Applications with a Time-interleaved Architecture | |
Long Zhao ; Yuhua Cheng | |
2016 | |
关键词 | summarized mostly blocks designing settling challenges offset mainstream calibration switching summarized mostly blocks designing settling challenges offset mainstream calibration switching |
英文摘要 | The time-interleaved(TI) architecture is used for ultra-high speed ADC applications. For designing a single-channel ADC for TI architecture applications, SAR ADCs becomes popular due to the features such as mostly digital logic, small chip area and power efficient etc. This paper reviews techniques for designing high-speed single-channel SAR ADCs in CMOS technology to implement a high speed ADC with TI architecture. The techniques are summarized at both the architecture and building blocks levels. Design challenges and circuit considerations are discussed. A summary of the state-of-the-art high-speed single-channel SAR ADCs are also provided.; The time-interleaved(TI) architecture is used for ultra-high speed ADC applications. For designing a single-channel ADC for TI architecture applications, SAR ADCs becomes popular due to the features such as mostly digital logic, small chip area and power efficient etc. This paper reviews techniques for designing high-speed single-channel SAR ADCs in CMOS technology to implement a high speed ADC with TI architecture. The techniques are summarized at both the architecture and building blocks levels. Design c; IEEE Beijing Section; 4 |
语种 | 英语 |
内容类型 | 其他 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/479817] |
专题 | 信息科学技术学院 |
推荐引用方式 GB/T 7714 | Long Zhao,Yuhua Cheng. Design Considerations of SAR ADCs in CMOS Technology for High Speed Circuit Applications with a Time-interleaved Architecture, Design Considerations of SAR ADCs in CMOS Technology for High Speed Circuit Applications with a Time-interleaved Architecture. 2016-01-01. |
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