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	Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond; Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond
	Gong Chen ; Ming Li ; Jiayang Zhang ; Yuancheng Yang ; Ru Huang
	2016
关键词	drain immunity spacer dielectric capacitance doping graded TCAD acceptable parasitic drain immunity spacer dielectric capacitance doping graded TCAD acceptable parasitic
英文摘要	In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain(AGLDD) exhibits very good SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer material and optimizing drain spacer width, preferable SCE immunity and higher overdrive current are achieved while parasitic capacitance can be maintained in an acceptable range. This scheme provides a feasible guideline for future low power vertical channel nanowire FETs design.; In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain(AGLDD) exhibits very good SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer material and optimizing drain spacer width, preferable SCE immunity and higher overdrive current are achieved; IEEE Beijing Section; 3
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/479777]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Gong Chen,Ming Li,Jiayang Zhang,et al. Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond, Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond. 2016-01-01.

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