Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and   Bump-Containing Chip-on-Chip Integration

doi:10.1109/TCPMT.2017.2695647

CORC > 北京大学 > 信息科学技术学院

	Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration
	Guan, Yong ; Zhu, Yunhui ; Ma, Shenglin ; Zeng, Qinghua ; Chen, Jing ; Jin, Yufeng
刊名	IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
	2017
关键词	3-D packaging chip-on-chip (CoC) integration reliability through silicon via (TSV) wafer-on-wafer (WoW) integration PIEZORESISTIVE STRESS SENSOR THROUGH-SILICON RELIABILITY INTERCONNECTS VOLUME VIAS
DOI	10.1109/TCPMT.2017.2695647
英文摘要	This paper develops a bumpless wafer-on-wafer (WoW) memory integration approach in order to increase its throughput and reliability without sacrificing the electrical and mechanical performances compared to the bump-containing chip-on-chip (CoC) integration. The features are that through silicon vias are bottom-up filled after multilayer wafers bonding and connected to the predeposited redistribution layers on the front side of each wafer simultaneously. A given mass of four-layer bumpless WoW integration samples and bump-containing CoC integration samples is fabricated. The electrical testing, X-ray inspection, cross-section observation, stress testing, and thermal cycling testing are employed in order to compare the characterization of the two integration approaches. All test results support that there is a better performance, higher throughput, and lower cost in the proposed bumpless WoW integration approach, which indicates that this proposed approach may be a good candidate for memories-stacking application.; National Natural Science Foundation of China [U1537208]; SCI(E); ARTICLE; 7; 1011-1019; 7
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/472286]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Guan, Yong,Zhu, Yunhui,Ma, Shenglin,et al. Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration[J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,2017.
APA	Guan, Yong,Zhu, Yunhui,Ma, Shenglin,Zeng, Qinghua,Chen, Jing,&Jin, Yufeng.(2017).Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration.IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY.
MLA	Guan, Yong,et al."Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration".IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY (2017).