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	Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer; Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer
	Rui Jin ; Yuncheng Song ; Min Ji ; Honghua Xu ; Jinfeng Kang ; Ruqi Han ; Xiaoyan Liu
	2008
关键词	Buffer transistor ferroelectric simulator stack drain scaling insulator gradation dielectric Buffer transistor ferroelectric simulator stack drain scaling insulator gradation dielectric
英文摘要	The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer layer.Different configurations of gate stack are simulated and analyzed.It is shown that the stru...; The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer layer.Different configurations of gate stack are simulated and analyzed.It is shown that the stru...; IEEE Beijing Section、Chinese Institute of Electronics (CIE); 4
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/450956]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Rui Jin,Yuncheng Song,Min Ji,et al. Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer, Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer. 2008-01-01.

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