Low Temperature Multi-layer Wafer Level Package for Chip Scale Atomic Clock (CSAC) | |
Li, Nannan ; Zhang, Yangxi ; Zhu, Ningli ; Zhu, Yunhui ; Gao, Chengchen ; Chen, Jing | |
2015 | |
关键词 | multi-layer bonding wafer level package anodic bonding BCB adhesive bonding CSAC |
英文摘要 | This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature (400 degrees C). The triple structure is supported by two silicon wafers. It is realized by photosensitive BCB adhesive bonding with good uniformity, relatively high mechanical strength (8Mpa) and low bonding temperature (250 degrees C). The results show that over 60% of wafer is bonded with no void on the joint area and well aligned. At last, the stacked wafer is diced into individual chips.; CPCI-S(ISTP); j.chen@pku.edu.cn; 481-484 |
语种 | 英语 |
出处 | IEEE 10th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS) |
内容类型 | 其他 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/450211] |
专题 | 信息科学技术学院 |
推荐引用方式 GB/T 7714 | Li, Nannan,Zhang, Yangxi,Zhu, Ningli,et al. Low Temperature Multi-layer Wafer Level Package for Chip Scale Atomic Clock (CSAC). 2015-01-01. |
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