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	A 1-V 23-��W 88-dB DR Sigma-Delta ADC for high-accuracy and low-power applications
	Zhao, Long ; Deng, Chenxi ; Chen, Hongming ; Wang, Guan ; Cheng, Yuhua
	2015
英文摘要	A 1-V 23-��W Sigma-Delta ADC for high-accuracy and low-power applications is presented in a standard 0.18-��m CMOS technology. To achieve high accuracy with low power consumption in low voltage environment, the proposed modulator is implemented with a 1-bit 3rd-order topology, in which the input-feedforward structure and switched-opamp technique are combined. Meanwhile, a pseudo RAM architecture is proposed for the decimation filter. The ADC achieves 88-dB DR over a 300-Hz bandwidth with an OSR of 128, while it consumes 23��W and occupies 0.69mm2. ? 2015 IEEE.; EI
语种	英语
出处	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
DOI标识	10.1109/ASICON.2015.7517011
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449300]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhao, Long,Deng, Chenxi,Chen, Hongming,et al. A 1-V 23-��W 88-dB DR Sigma-Delta ADC for high-accuracy and low-power applications. 2015-01-01.

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