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	Electrical Simulation and Analysis of Si Interposer for 3D IC Integration
	Sun, Xin ; Miao, Min ; Zhu, Yunhui ; Fang, Runiu ; Wang, Guanjiang ; Lu, Wengao ; Chen, Jing ; Jin, Yufeng
	2014
关键词	SEGMENTATION METHOD 3-D ICS SILICON TSV
英文摘要	This paper focuses on the electrical simulation and analysis of silicon interposer. Basic interconnect elements such as TSV and RDL are simulated and verified with measurement results, electrical parameters are extracted and analyzed. Segmentation is used in long signal path modeling to improve simulation efficiency with a fine accuracy. Silicon interposer is segmented into many interconnect pieces. Parasitic RLCGs of each segment are extracted and interconnected to form the whole circuit model of Si interposer. A Silicon interposer for a 4-SRAM module integration, proposed and implemented as a leading demo for a Logic+Memory high-speed digital signal processing module, was used as a test vehicle for the modeling and analysis methodologies mentioned.; EI; CPCI-S(ISTP); miaomin@ime.pku.edu.cn; 2099-2103
语种	英语
出处	2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)
DOI标识	10.1109/ECTC.2014.6897592
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/423973]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Sun, Xin,Miao, Min,Zhu, Yunhui,et al. Electrical Simulation and Analysis of Si Interposer for 3D IC Integration. 2014-01-01.

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