Mechanical and Electrical Reliability Assessment of Bump-less Wafer-on-Wafer Integration with One-time Bottom-up TSV Filling | |
Guan, Yong ; Zhu, Yunhui ; Zeng, Qinghua ; Ma, Shenglin ; Su, Fei ; Bian, Yuan ; Zhong, Xiao ; Chen, Jing ; Jin, Yufeng | |
2015 | |
关键词 | INTERPOSER STACKING |
英文摘要 | Three-dimensional (3D) stacked memory module based on TSV is becoming an attractive alternative. Chips are assembled through micro bumps, which will bring additional thermo-mechanical stress, as well as the channel resistance and interconnection reliability problem. In this paper, we leverage thermal cycles to assess the mechanical and electrical reliability of a bump-less wafer-on-wafer integration approach with one-time bottom-up TSV filling we reported. Resistance was measured by four-point probes test after 10, 20, 40, 80, 160, 240, 320..., until 640 thermal cycles. Part of fixed TSVs' morphology was observed through scanning electron microscope (SEM) and stress was qualitative characterized by an infrared photo elastic system during thermal cycles. What's more, a thermo-mechanical finite element model (FEM) simulation was discussed, which showed that there was little difference in stress, strain, and copper extrusion values at lower temperature. All test results supported the good mechanical and electrical behavior of this bump-less wafer-on-wafer integration approach.; EI; CPCI-S(ISTP); j.chen@pku.edu.cn; 816-821; 2015-July |
语种 | 英语 |
出处 | 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) |
DOI标识 | 10.1109/ECTC.2015.7159686 |
内容类型 | 其他 |
源URL | [http://ir.pku.edu.cn/handle/20.500.11897/423743] |
专题 | 信息科学技术学院 |
推荐引用方式 GB/T 7714 | Guan, Yong,Zhu, Yunhui,Zeng, Qinghua,et al. Mechanical and Electrical Reliability Assessment of Bump-less Wafer-on-Wafer Integration with One-time Bottom-up TSV Filling. 2015-01-01. |
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