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	3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation
	Yu, Shimeng ; Chen, Hong-Yu ; Deng, Yexin ; Gao, Bin ; Jiang, Zizhen ; Kang, Jinfeng ; Wong, H.-S. Philip
	2013
英文摘要	3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t m) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11?? higher than a 2D array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials. ? 2013 JSAP.; EI; 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/410727]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yu, Shimeng,Chen, Hong-Yu,Deng, Yexin,et al. 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. 2013-01-01.

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