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	Time Divided Architecture for Closed Loop MEMS Capacitive Accelerometer
	Huang, Jingqing ; Zhang, Tingting ; Zhao, Meng ; Hong, Lichen ; Zhang, Yacong ; Lu, Wengao ; Chen, Zhongjian ; Hao, Yilong
	2012
英文摘要	This paper mainly discusses issues concerning the architecture of time divided closed loop accelerometer. For this particular architecture mathematical relationship between the external acceleration detected by sensor and the voltage output of the readout circuits is deduced. Both Matlab/Simulink model and Verilog-A model for such architecture are established. Simulation results agree with the mathematical formula. Readout circuits designed to work under 50kHz with feedback duty cycle 11 being 60% are fabricated using 0.35 mu m HV CMOS process. Test results show a sensitivity of 1.518V/g.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000319824700129&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/405894]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Huang, Jingqing,Zhang, Tingting,Zhao, Meng,et al. Time Divided Architecture for Closed Loop MEMS Capacitive Accelerometer. 2012-01-01.

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