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	A customized design of DRAM controller for on-chip 3D DRAM stacking
	Zhang, Tao ; Wang, Kui ; Feng, Yi ; Song, Xiaodi ; Duan, Lian ; Xie, Yuan ; Cheng, Xu ; Lin, Youn-Long
	2010
英文摘要	To address the 'memory wall' challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins. To demonstrate the feasibility of 3D memory stacking, this paper introduces a customized 3D Double-Data-Rate (DDR) SDRAM controller design, which communicates with DRAM layers by TSVs. In addition, we propose a parallel access policy to further improve the performance. The 3D DDR controller is integrated in a 3D stacking System-on-Chip (SoC) architecture, where a high-bandwidth 3D DRAM chip is stacked on the top. The 3D SoC is divided into two logic layers with each having an area of 2.5 ?? 5.0mm2, with a 3-layer 2Gb DRAM stacking. The whole chip has been fabricated in Chartered 130nm low-power process and Tezzaron's 3D bonding technology. The simulation result shows that the on-chip DRAM controller can run as fast as 133MHz and provide 4.25GB/s data bandwidth in a single channel and 8.5GB/s with parallel access policy.1 ? 2010 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/CICC.2010.5617465
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/329531]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhang, Tao,Wang, Kui,Feng, Yi,et al. A customized design of DRAM controller for on-chip 3D DRAM stacking. 2010-01-01.

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