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	Design and analysis of low-voltage silicon-controlled rectifier ESD protection circuit
	Shi, Zitao ; Liu, Jian ; Wang, Xin ; Lin, Lin ; Wang, Albert ; Cheng, Yuhua ; Yang, Li-Wu
	2010
英文摘要	This paper reports design and analysis of new low triggering voltage dual-polarity silicon-controlled rectifier (SCR) ESD protection structures and circuits in CMOS. Design optimization technique enables flexible ESD triggering voltage (Vt1), ESD holding voltage (Vh) and ESD protection capability. Measurements show very low and adjustable Vt1, low leakage (I1eak), low noise figure (NF), low ESD-induced parasitic capacitance (CESD) and fast ESD triggering time (t1). It achieves high ESD protection to Si ratio of ESDV??6.83V/??m2. ? 2010 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/EDSSC.2010.5713722
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295482]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Shi, Zitao,Liu, Jian,Wang, Xin,et al. Design and analysis of low-voltage silicon-controlled rectifier ESD protection circuit. 2010-01-01.

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