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	Variability investigation of gate-all-around silicon nanowire transistors from top-down approach
	Huang, R. ; Wang, R.S. ; Zhuge, J. ; Yu, T. ; Ai, Y.J. ; Fan, C. ; Pu, S.S. ; Zou, J.B. ; Huang, X. ; Wang, Y.Y.
	2010
英文摘要	The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses the process impact on nanowire LER/LWR, as well as the impact of 2D nanowire LER on performance variation and degradation. And it is found that SNWTs, which is immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF which is enhanced by diameter-dependent annealing. In addition, the different impacts of the experimentally extracted variation sources in SNWTs on the threshold voltage and on current flucturation is discussed, as well as the variability impact on SNWT based SRAM cells compared with planar SRAM cells. ? 2010 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/EDSSC.2010.5713789
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/295461]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Huang, R.,Wang, R.S.,Zhuge, J.,et al. Variability investigation of gate-all-around silicon nanowire transistors from top-down approach. 2010-01-01.

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