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	A Novel Frequency Search Algorithm to Achieve Locking Without Phase Tracking in ADPLL
	Wu, Bohan ; Gai, Weixin ; Han, Te
	2013
关键词	ALL-DIGITAL PLL LOCKED LOOP MULTIPLICATION SYNTHESIZER CMOS TIME
英文摘要	A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL ( ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word ( NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly affect the accuracy of the calculation, the output frequency is continuously measured and frequency error is averaged to minimize those impacts. With 0.13um CMOS process, the proposed ADPLL operates at 2.7 GHz and achieves 0.35 us locking time while consuming 7.47mW.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000332006802170&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; CPCI-S(ISTP); 4
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/292520]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wu, Bohan,Gai, Weixin,Han, Te. A Novel Frequency Search Algorithm to Achieve Locking Without Phase Tracking in ADPLL. 2013-01-01.

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