QQ客服 官方微博 反馈留言

	A Dual Loop Dual VCO CMOS PLL Using a Novel Coarse Tuning Technique for DTV
	Shi, Congyin ; Yang, Huaizhou ; Xiao, Huiling ; Liu, Junhua ; Liao, Huailin
	2008
关键词	phase-locked loops adaptive frequency calibration dual VCO phase noise dual loop FREQUENCY-SYNTHESIZER
英文摘要	A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of I MHz and settles in less than 180 mu s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency calibration (AFC) of programmable dichotomizing coarse tuning technology is integrated. The novel AFC structure uses pulses of 2(n) times of the PFD's reference frequency for counting and comparison. Two multi-band voltage controlled oscillators, which cover 866 to 1468 MHz and 1282 to 1892 MHz separately, are implemented so as to reduce VCO output noise and power consumption by reducing VCO gain on each frequency turning curse. I/Q carriers are generated by VCO output divided by 2. Fabricated in 0.18-mu m CMOS technology, the PLL achieves phase noise of less than -132dBc/Hz at 1.45 MHz offset.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000265971002075&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/ICSICT.2008.4734882
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/153447]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Shi, Congyin,Yang, Huaizhou,Xiao, Huiling,et al. A Dual Loop Dual VCO CMOS PLL Using a Novel Coarse Tuning Technique for DTV. 2008-01-01.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。