Detection System of Single Event Upset Based onFPGA
Bobo Feng; Cuiping Shao; Huiyun Li
2018
会议日期2018
会议地点中国厦门
英文摘要As the semiconductor process progresses into deep submicron nodes, single event upsets (SEUs) have severely deteriorated the reliability of Integrated circuits (ICs), especially for the satellite electronic equipment. Traditional methods of SEU is radiation scanning with fine resolutions over the surface for inspection, which is just sample test with workload statistics and experiences as the qualitative criterion, thus results in costly, time-consuming and error-prone test procedures. In this paper, we propose a SEU detection system based on FPGA by using the controllability and observability of scan chain, which can automatically generate test vectors for scan chain of DUT (design under test), analyze test results and synchronize irradiation source and DUT. Our proposed detection system not only reduce the cost of testing, but also increase the flexibility of testing. The proposed system can automatically detect the reliability of DUT and count the number of soft errors caused by SEU with low cost overhead. Experimental results on ISCAS'89 benchmark circuits implementation demonstrate the validity of this method.
内容类型会议论文
源URL[http://ir.siat.ac.cn:8080/handle/172644/13741]  
专题深圳先进技术研究院_集成所
推荐引用方式
GB/T 7714
Bobo Feng,Cuiping Shao,Huiyun Li. Detection System of Single Event Upset Based onFPGA[C]. 见:. 中国厦门. 2018.
个性服务
查看访问统计
相关权益政策
暂无数据
收藏/分享
所有评论 (0)
暂无评论
 

除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。


©版权所有 ©2017 CSpace - Powered by CSpace