| A parallel architecture using discrete wavelet transform for fast ICA implementation (CPCI-S收录) | |
| Huang, RB; Cheung, YM; Zhu, SM | |
| 会议名称 | PROCEEDINGS OF 2003 INTERNATIONAL CONFERENCE ON NEURAL NETWORKS & SIGNAL PROCESSING, PROCEEDINGS, VOLS 1 AND 2 |
| URL标识 | 查看原文 |
| 内容类型 | 会议论文 |
| URI标识 | http://www.corc.org.cn/handle/1471x/2140449 |
| 专题 | 华南理工大学 |
| 作者单位 | GuangDong Pharmaceut Coll, Dept Math, Guangzhou, Peoples R China |
| 推荐引用方式 GB/T 7714 | Huang, RB,Cheung, YM,Zhu, SM. A parallel architecture using discrete wavelet transform for fast ICA implementation (CPCI-S收录)[C]. 见:PROCEEDINGS OF 2003 INTERNATIONAL CONFERENCE ON NEURAL NETWORKS & SIGNAL PROCESSING, PROCEEDINGS, VOLS 1 AND 2. |
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