Neural network approach for multiple fault test of digital circuit (CPCI-S收录) | |
Pan Zhongliang[1]; Chen Ling[1]; Liu Shouqiang[1]; Zhang Guangzhao[2] | |
会议名称 | ISDA 2006: SIXTH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS DESIGN AND APPLICATIONS, VOL 3 |
URL标识 | 查看原文 |
内容类型 | 会议论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/2114333 |
专题 | 华南理工大学 |
作者单位 | 1.[1]South China Univ Technol, Dept Elect, Guangzhou 510631, Peoples R China 2.[2]Zhongshan Univ, Dept Elect, Guangzhou 510275, Peoples R China |
推荐引用方式 GB/T 7714 | Pan Zhongliang[1],Chen Ling[1],Liu Shouqiang[1],等. Neural network approach for multiple fault test of digital circuit (CPCI-S收录)[C]. 见:ISDA 2006: SIXTH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS DESIGN AND APPLICATIONS, VOL 3. |
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