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	Analytic potential model for asymmetricunderlap gate-all-around MOSFET (CPCI-S收录)
	Wang, Shaodi[1,2]; Guo, Xinjie[1,2]; Zhang, Lining[2]; Zhang, Chenfei[1,2]; Liu, Zhiwei[2]; Wang, Guozeng[2]; Zhang, Yang[2]; Wu, Wen[2]; Zhao, Xiaojin[2]; Wang, Wenping[2]
会议名称	NANOTECHNOLOGY 2011: ELECTRONICS, DEVICES, FABRICATION, MEMS, FLUIDICS AND COMPUTATIONAL, NSTI-NANOTECH 2011, VOL 2
关键词	asymmetric underlap misalinment gate-all-around
URL标识	查看原文
内容类型	会议论文
URI标识	http://www.corc.org.cn/handle/1471x/2058458
专题	华南理工大学
作者单位	1.[1]Peking Univ, Shenzhen Grad Sch, Sch Comp & Informat Engn, Key Lab Integrated Microsyst, Shenzhen 518055, Peoples R China 2.[2]Peking Univ, Shenzhen SOC Key Lab, PKU HKUST Shenzhen Inst, Shenzhen 518057, Peoples R China
推荐引用方式 GB/T 7714	Wang, Shaodi[1,2],Guo, Xinjie[1,2],Zhang, Lining[2],等. Analytic potential model for asymmetricunderlap gate-all-around MOSFET (CPCI-S收录)[C]. 见:NANOTECHNOLOGY 2011: ELECTRONICS, DEVICES, FABRICATION, MEMS, FLUIDICS AND COMPUTATIONAL, NSTI-NANOTECH 2011, VOL 2.

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