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	基于数字ASIC设计流程的DDS设计与实现; Design and Implementation of DDS Based on Digital ASIC Design Flow
	陈冀明 ; 李开航
	2010
关键词	DDS ASIC Verilog 流水线 DDS ASIC Verilog pipeline
英文摘要	作为第三代频率合成技术,直接数字频率合成器具有显著的优点并得到广泛的应用。在此结合数字ASIC设计流程,利用流水线技术和函数对称性性质,设计并实现一个优化的ddS电路。从系统结构划分到自动布局布线,逐步介绍各个设计阶段的目的、使用软件及设计要点。经过分析,最终得到的ddS电路能够运行在150 MHz系统时钟下,并且具有较小的面积,满足设计要求。; As the third generation frequency synthesizer,Direct Digital Synthesizer(DDS) has been widely used due to its many significant advantages.An optimized DDS based on digital ASIC design flow is designed and implemented by using the pipeline technology and the symmetry character of a few functions.The design steps from the structure divide to the auto placement and route are given out in detail,and each involves in the design purpose,software in use and design points.Theoretical results show that the proposed DDS has advantages of small size and can run at 150 MHz clock frequency,which meets requirement of the design.
语种	zh_CN
内容类型	期刊论文
源URL	[http://dspace.xmu.edu.cn/handle/2288/127088]
专题	物理技术－已发表论文
推荐引用方式 GB/T 7714	陈冀明,李开航. 基于数字ASIC设计流程的DDS设计与实现, Design and Implementation of DDS Based on Digital ASIC Design Flow[J],2010.
APA	陈冀明,&李开航.(2010).基于数字ASIC设计流程的DDS设计与实现..
MLA	陈冀明,et al."基于数字ASIC设计流程的DDS设计与实现".(2010).

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