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	Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system
	LIU LeiBo ; CHEN YingJie ; YIN ShouYi ; ZHOU Li ; YUAN Hang ; WEI ShaoJun ; LIU LeiBo ; CHEN YingJie ; YIN ShouYi ; ZHOU Li ; YUAN Hang ; WEI ShaoJun
	2016-03-30 ; 2016-03-30
关键词	AVS video decoder coarse-grained reconfigurable multimedia system computation-intensive tasks parallelization and pipelining HW/SW partitioning TN919.81
其他题名	Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system
中文摘要	In this paper,a TPP(Task-based Parallelization and Pipelining)scheme is proposed to implement AVS(Audio Video coding Standard)video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia system.An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning.Several parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS decoder.Also,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct)and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of REMUS.Owing to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile)1920�088@39fps streams when exploiting a 200 MHz working frequency.; In this paper,a TPP(Task-based Parallelization and Pipelining) scheme is proposed to implement AVS(Audio Video coding Standard) video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia system.An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning.Several parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS decoder.Also,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct) and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of REMUS.Owing to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile) 1920�088@39fps streams when exploiting a 200 MHz working frequency.
语种	英语 ; 英语
内容类型	期刊论文
源URL	[http://ir.lib.tsinghua.edu.cn/ir/item.do?handle=123456789/147038]
专题	清华大学
推荐引用方式 GB/T 7714	LIU LeiBo,CHEN YingJie,YIN ShouYi,et al. Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system[J],2016, 2016.
APA	LIU LeiBo.,CHEN YingJie.,YIN ShouYi.,ZHOU Li.,YUAN Hang.,...&WEI ShaoJun.(2016).Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system..
MLA	LIU LeiBo,et al."Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system".(2016).

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