| 布线图案导致的集成电路平坦化损伤研究 | |
| 郭玉龙 ; 郭丹 ; 潘国顺 ; 雒建斌 ; GUO Yulong ; GUO Dan ; PAN Guoshun ; LUO Jianbin | |
| 2016-03-30 ; 2016-03-30 | |
| 关键词 | 化学机械抛光 集成电路制造 平坦化损伤 低k介质 互连结构 抛光下压力 CMP IC manufacturing flatten damages low-k dielectric interconnect structure polishing pressure TN405 |
| 其他题名 | Research on the damages of integrated circuit(IC) chip induced by wiring pattern in planarization |
| 中文摘要 | 使用化学机械抛光(CMP)的方式,对商用芯片进行拆解,获得了不同制造工艺的铜/低k介质互连结构样品。通过对所获得的32 nm制造工艺的铜/低k介质互连结构样品进行进一步的化学机械抛光实验来研究抛光过程中出现的损伤。实验结果发现,抛光压力过大和过小分别会造成宏观缺陷和导线腐蚀,互连线的分布会导致导线自身的碟型缺陷、不同图案布线结构交界两侧明显的表面高度差异以及同一图案布线结构内部的表面周期性高度起伏。这种表面高度差异可以通过预补偿的方式得到一定的改善。; Some commercial CPU chips were disassembled with the chemical mechanical polishing(CMP) method to achieve Cu/low-k interconnect structures with different manufacturing techniques. The Cu/low-k interconnect structures with manufacturing technique of 32 nm were polished further to study the damages occured in the chemical mechanical polishing process. The results show that the larger and smaller polishing pressures lead to the macroscopic defects and wire erosions separately. In addition, wiring pattern distribution would result in the dishing effects of wires, the obvious difference in surface height at the sides of different wiring pattern joints and the surface height changing in periods of the same wiring pattern, this surface height difference would be improved with the pre-offset method. |
| 语种 | 中文 ; 中文 |
| 内容类型 | 期刊论文 |
| 源URL | [http://ir.lib.tsinghua.edu.cn/ir/item.do?handle=123456789/144673]  |
| 专题 | 清华大学 |
| 推荐引用方式 GB/T 7714 | 郭玉龙,郭丹,潘国顺,等. 布线图案导致的集成电路平坦化损伤研究[J],2016, 2016. |
| APA | 郭玉龙.,郭丹.,潘国顺.,雒建斌.,GUO Yulong.,...&LUO Jianbin.(2016).布线图案导致的集成电路平坦化损伤研究.. |
| MLA | 郭玉龙,et al."布线图案导致的集成电路平坦化损伤研究".(2016). |
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