A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

CORC > 半导体研究所 > 中国科学院半导体研究所 > 中国科学院半导体研究所（2009年前）

	A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC
	Hao Zhikun
刊名	半导体学报
	2009
卷号	30 期号:9 页码:66-69
中文摘要	this paper presents a high speed rom-less direct digital frequency synthesizer (ddfs) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. a 10-bit nonlinear segmented dac is used in place of the rom look-up table for phase-to-sine amplitude conversion and the linear dac in a conventional ddfs.the design procedure for implementing the nonlinear dac is presented. to ensure high speed, current mode logic (cml) is used. the chip is implemented in chartered 0.35μm coms technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mw at a single 3.3 v supply voltage. the maximum operating frequency is 850 mhz at room temperature and 1.0 ghz at 0 ℃.
学科主题	人工智能
收录类别	CSCD
语种	英语
公开日期	2010-11-23
内容类型	期刊论文
源URL	[http://ir.semi.ac.cn/handle/172111/15713]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Hao Zhikun. A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC[J]. 半导体学报,2009,30(9):66-69.
APA	Hao Zhikun.(2009).A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC.半导体学报,30(9),66-69.
MLA	Hao Zhikun."A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC".半导体学报 30.9(2009):66-69.