A novel noise optimization technique for inductively degenerated CMOS LNA

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	A novel noise optimization technique for inductively degenerated CMOS LNA
	Geng Zhiqing ; Wang Haiyong ; Wu Nanjian
刊名	半导体学报
	2009
卷号	30 期号:10 页码:137-142
中文摘要	this paper proposes a novel noise optimization technique. the technique gives analytical formulae for the noise performance of inductively degenerated cmos low noise amplifier (lna) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. lna circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. we design a 1.8 ghz lna in a tsmc 0.25 pan cmos process. the measured results show a noise figure of 1.6 db with a forward gain of 14.4 db at a power consumption of 5 mw, demonstrating that the designed lna circuits can achieve low noise figure levels at low power dissipation.
学科主题	半导体物理
收录类别	CSCD
资助信息	the national natural science foundation of china,the state key development program for basic research of china
语种	英语
公开日期	2010-11-23
内容类型	期刊论文
源URL	[http://ir.semi.ac.cn/handle/172111/15693]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Geng Zhiqing,Wang Haiyong,Wu Nanjian. A novel noise optimization technique for inductively degenerated CMOS LNA[J]. 半导体学报,2009,30(10):137-142.
APA	Geng Zhiqing,Wang Haiyong,&Wu Nanjian.(2009).A novel noise optimization technique for inductively degenerated CMOS LNA.半导体学报,30(10),137-142.
MLA	Geng Zhiqing,et al."A novel noise optimization technique for inductively degenerated CMOS LNA".半导体学报 30.10(2009):137-142.